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10 mhz, 20 v/ s, g = 1, 2, 5, 10 i cmos programmable gain instrumentation amplifier data sheet ad8250 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2007 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features small p ackage: 10 - l ead msop programmable g ains: 1, 2, 5, 10 digital or p in - programmable gain setti ng wide s upply: 5 v to 15 v excellent dc performance high cmrr 98 db (min imum ), g = 10 low gain drif t: 10 ppm/ c (max imum ) low offset dri ft: 1 .7 v/ c (max imum ) , g = 10 excellent ac performance fast settl ing t ime: 615 n s to 0.0 0 1% (max imum ) high slew ra te: 20 v/s (min imum ) low d istortion: ?110 db thd at 1 khz high cmrr over f requency: 80 db to 50 khz (min imum ) low n oise: 18 nv / hz, g = 10 (max imu m ) low p ower: 4 .1 ma applications data a cquisition bio m edical a nalysis test and m easurement general description the ad8250 is an instrumentation amplifier with digitally programmable gains that has g? input impedance, low output noise, and low distortion making it suitable for interfacing with sensor s an d driving high sam ple rate analog - to - digital converters (adcs). it has a high bandwidth of 10 mhz, low thd of ?110 db and fast settling time of 615 ns (max imum ) to 0.001%. offset drift and gain drift are g uaranteed to 1.7 v/c and 10 ppm/c, respectively , for g = 10 . in addition to its wide input common voltage range, it boasts a high common - mode rejection of 80 db at g = 1 from dc to 50 khz. the combination of precision dc performance coupled with high sp eed capabilities make s the ad8250 an excellent candidate for data acquisition. furthermore, this monolithic solution simplifies design and manufacturing and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplif iers. the ad8250 user interface consists of a parallel port that allows u sers to set the gain in one of two ways (see figure 1 ). a 2 - bit word sent via a bus can be latched using the wr input. an alternative is t o use the transparent gain mode where the state of the logic levels at the gain port determine s the gain. functional block dia gram a1 a0 dgnd wr ad8250 +v s ?v s ref out +in logic ?in 06288-001 1 10 8 3 7 4 5 6 2 9 figure 1. 25 ?10 ?5 0 5 10 15 20 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-023 figure 2 . gain vs. frequency table 1 . instrumentation amplifiers by category general purpose zero drift mil grade low power high speed pga ad8220 1 ad8231 1 ad620 ad627 1 ad8250 ad8221 ad8553 1 ad621 ad623 1 ad8251 ad8222 ad8555 1 ad524 ad8223 1 ad8253 ad8224 1 ad8556 1 ad526 ad8228 ad8557 1 ad624 1 rail - to - rail output. the ad8250 is available in a 10 - lead msop package and is specified over the ?40c to +85c temperature range, making it an excellent solution for applications where size and packing density are important considerations.
ad8250 data sheet rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 function al block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing di agram ........................................................................... 5 absolute maximum ratings ............................................................ 6 maximum power dissipation ..................................................... 6 e sd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 15 gain selection ............................................................................. 15 power supply regulation and bypassing ................................ 17 input bias current return path ............................................... 17 input protection ......................................................................... 17 reference terminal .................................................................... 18 common - mode input voltage range ..................................... 18 layout .......................................................................................... 18 rf interference ........................................................................... 19 driving an adc ......................................................................... 19 applications ..................................................................................... 20 differential output .................................................................... 20 setting gains with a microcontroller ...................................... 20 data acquisition ......................................................................... 21 outline dime nsions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 5 /1 3 rev. b to rev. c changed 49.9 to 100 in driving an adc section and figure 55 .......................................................................................... 19 1 1 /10 rev. a to rev. b changes to voltage offset, offset rti v os , average temperature coefficient parameter in table 2 ............................. 3 updated outline dimensions ....................................................... 22 5 /08 rev. 0 to rev. a changes to table 1 ............................................................................ 1 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................. 6 add ed figure 17; renumbered sequentially ................................. 9 changes to figure 23 ...................................................................... 10 changes to figure 24 to figure 26 ................................................ 11 add ed figure 29 ............................................................................. 11 changes to figure 31 ...................................................................... 12 deleted figure 4 3 to figure 4 6; renumbered sequentially ...... 14 inserted figure 4 5 and figure 46 .................................................. 14 changes to timing for latched gain mode section ................. 1 6 changes to layout section and coupling noise section .......... 1 8 changes to figure 59 ...................................................................... 21 1 /0 7 revision 0: initial version
data sheet ad8250 rev. c | page 3 of 24 specifications + v s = 15 v, ? v s = ? 1 5 v, v ref = 0 v @ t a = 25 c, g = 1, r l = 2 k?, unless otherwise noted. table 2 . parameter conditions min typ max unit common - mode rejection ratio (cmrr) cmrr to 60 hz with 1 k? source imbalance +in = ? in = ?10 v to +10 v g = 1 80 9 8 db g = 2 86 104 db g = 5 94 1 10 db g = 10 98 1 10 db cmrr to 5 0 khz +in = ? in = ?10 v to +10 v g = 1 80 db g = 2 86 db g = 5 90 db g = 10 90 db noise voltage noise, 1 khz , rti g = 1 40 nv/hz g = 2 27 nv/hz g = 5 21 nv/hz g = 10 18 nv/hz 0.1 hz to 10 hz , rti g = 1 2.5 v p -p g = 2 2.5 v p -p g = 5 1.5 v p -p g = 10 1.0 v p -p current noise , 1 khz 5 p a/hz current noise, 0.1 hz to 10 hz 60 pa p -p voltage offset offset rti v os g = 1, 2, 5, 10 (70 + 200/g) (200 + 600/g) v over temperature t = ?40c to +85c (90 + 300/g) (260 + 900/g) v average t emperature c oefficient t = ?40c to +85c ( 0.6 + 1.5/g) (1.2 + 5/g) v/c offset r eferred to the input vs. supply (psr) v s = 5 v to 15 v (2 + 7/g) (6 + 20/g) v/v input current input bias current 5 30 na over t emperature t = ?40c to +85c 40 na average temperature coefficient t = ?40c to +85c 400 pa/c input offs et current 5 30 na over t emperature t = ?40c to +85c 30 na average temperature coefficient t = ?40c to +85c 160 pa/c dynamic response small signal ?3 db bandwidth g = 1 10 mhz g = 2 10 mhz g = 5 10 mhz g = 10 3 mhz settling time 0.01% out = 10 v step g = 1 5 85 n s g = 2 605 n s g = 5 605 n s g = 10 648 n s
ad8250 data sheet rev. c | page 4 of 24 parameter conditions min typ max unit settling time 0.001% out = 10 v step g = 1 6 15 ns g = 2 635 ns g = 5 635 ns g = 10 6 85 ns slew rate g = 1 20 v/ s g = 2 25 v/s g = 5 25 v/s g = 10 25 v/s total harmonic distortion f = 1 khz, r l = 10 k?, 10 v , g = 1 , 10 hz to 22 khz band - pass filter ? 110 db gain gain range g = 1, 2, 5, 10 1 10 v/v gain error out = 10 v g = 1 0 .03 % g = 2 , 5, 10 0.04 % gain nonlinearity out = ? 10 v to +10 v g = 1 r l = 10 k? , 2 k?, 600 ? 6 ppm g = 2 r l = 10 k?, 2 k?, 600 ? 8 ppm g = 5 r l = 10 k?, 2 k?, 600 ? 8 ppm g = 10 r l = 10 k?, 2 k?, 600 ? 1 0 ppm gain vs. temperature al l gains 10 ppm/c input input impedance differential 5.3||0.5 g? ||pf common mode 1.25||2 g? ||pf input operating voltage range v s = 5 v to 15 v ?v s + 1.5 +v s ? 1.5 v over temperature t = ?40c to +85c ?v s + 1.6 +v s ? 1.7 v ou tput output swing ?13.5 +13.5 v over temperature t = ?40c to +85c ?13.5 +13.5 v short - circuit current 37 ma reference input r in 20 k? i in +in, ?in, ref = 0 1 a voltage range ?v s +v s v gain to output 1 0.0001 v/v digi tal logic digital ground voltage, dgnd referred to gnd ?v s + 4.25 0 +v s ? 2.7 v digital input voltage low referred to gnd dgnd 2.1 v digital input voltage high referred to gnd 2.8 +v s v digital input current 1 a gain switching time 1 325 ns t su see figure 3 timing diagram 20 ns t hd see figure 3 timing diagram 10 ns t wr - low see figure 3 timing diagram 20 ns t wr - high see figure 3 timing diagram 40 ns
data sheet ad8250 rev. c | page 5 of 24 parameter conditions min typ max unit power supply operating range 5 15 v quiescent current, +i s 4.1 4.5 ma quiescent current, ?i s 3.7 4.5 ma over temperature t = ?40c to +85c 4.5 ma temperature range specified performance ?40 +85 c 1 add time for the output to slew and settle to calculate the total time for a gain change. timing diagram a0, a1 wr t su t hd t wr-high t wr-low 0 6288-057 figure 3. timing diagram for latched gain mode (see the timing for latched gain mode section)
ad8250 data sheet rev. c | page 6 of 24 absolute maximum rat ings table 3 . parameter rating supply voltage 17 v power dissipation see figure 4 output short - circuit current indefinite 1 common - mode in put voltage +v s + 13 v, ? v s ? 13 v differential input voltage +v s + 13 v, ? v s ? 13 v 2 digital logic inputs v s storage temperature range ? 65c to +125c operating temperature range 3 ? 40c to +85c lead temperature (soldering , 10 sec) 300c junction temperature 140 c ja ( f our - l ayer jedec standard board) 112 c/w package glass transition temperature 140c 1 assumes that the load is referenced to midsupply. 2 current must be kept to less than 6 ma. 3 temperature for specified performance is ? 40 c to +85c. for performance to 125c, see the typical performance characteristics section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this s pecification is not implied. exposure to absolute maximum r ating conditions for extended periods may affect device reliability. maximum power dissip ation the maximum s afe power dissipation in the ad 8250 package is limited by the associated rise in junction temperature (t j ) on the die. the plastic encapsulating the die locally reaches the junction temperature. at approximately 14 0c, which is the glass transition tempera ture, the plastic changes its prope r ties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, perm a nently shifting the parametric performance of the ad8250 . exceeding a junction temperature of 1 4 0c for an extended period can result in changes in silicon devices, p o tentially causing failure. the still - air thermal properties of the package and pcb ( ja ), the ambient temperature (t a ), and the total power dissipated in the package (p d ) determine the ju nction temperature of the die. the junction temperature is calculated as t j = t a + ( p d ja ) the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the pac k age due to the load drive for all outp uts. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). assuming that the load (r l ) is referenced to midsupply, the total drive power is v s /2 i out , some of which is diss i pated in the package and some in the load (v out i out ). the difference between the total drive power and the load power is the drive power dissipated in the package. p d = quiescent power + ( total drive power ? load power ) ( ) l out l out s s s d r v r v v i v p 2 C 2 ? ? ? ? ? ? ? ? + = in single - supply operation with r l referenced to ? v s , the worst case is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature on a four - layer jedec standard board . 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 ?40 ?20 120 100 80 60 40 20 0 maximum power dissipation (w) ambient temperature (c) 06288-004 figure 4 . maximum power dissipation vs. ambient temperature esd caution
data sheet ad8250 rev. c | page 7 of 24 pin configuration a nd function descript ions ?in dgnd ?v s a0 a1 +in ref +v s out wr ad8250 top view (not to scale) 1 2 3 4 5 10 9 8 7 6 06288-005 figure 5. pin configuration table 4 . pin function descriptions pin no. mnemoni c description 1 ? in inverting input terminal . true differential input. 2 dgnd digital ground. 3 ? v s negative supply terminal . 4 a0 gain setting pin (lsb) . 5 a1 gain setting pin (msb) . 6 wr write enable . 7 out output terminal . 8 +v s positive suppl y terminal . 9 ref reference voltage terminal . 10 +in non inverting input terminal . true differential input .
ad8250 data sheet rev. c | page 8 of 24 typical performance characteristics t a = 25c, +v s = +15 v, ?v s = ?15 v, r l = 10 k, unless otherwise noted. 06288-006 1400 1200 800 1000 600 400 200 0 number of units cmrr (v/v) ?120 ?90 ?60 ?30 0 30 60 90 120 figure 6. typical distribution of cmrr, g = 1 300 350 250 200 150 100 50 0 ?200 200 100 0 ?100 ?50 50 ?150 150 number of units offset voltage rti (v) 06288-007 figure 7. typical distributi on of offset voltage, v osi 600 500 400 300 200 100 0 ?30 30 10 20 0 ?10 ?20 number of units input bias current (na) 06288-008 figure 8. typical distributi on of input bias current 500 400 300 200 100 0 ?30 30 20 10 0 ?20 ?10 number of units input offset current (na) 06288-009 figure 9. typical distribution of input offset current 90 0 10 20 30 40 50 60 70 80 1 10 100 1k 10k 100k 06288-010 noise rti (nv/ hz) frequency (hz) g = 1 g = 2 g = 5 g = 10 figure 10. voltage spectral density noise vs. frequency 0 6288-011 1s/div 2v/div figure 11. 0.1 hz to 10 hz rti voltage noise, g = 1
data sheet ad8250 rev. c | page 9 of 24 06288-012 1s/div 1v/div figure 12 . 0.1 h z to 10 hz rti voltage noise, g = 10 18 0 2 4 6 8 10 12 14 16 1 10 100 1k 10k 100k 06288-013 current noise (pa/ hz) frequency (hz) figure 13 . current noise spectral density vs. frequency 06288-014 1s/div 140pa/div figure 14 . 0.1 hz to 10 hz current noise 150 130 110 90 70 50 30 10 1 10 100 1k 10k 100k 1m psrr (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-016 figure 15 . positive psrr vs. fre quency, rti 150 130 110 90 70 50 30 10 1 10 100 1k 10k 100k 1m psrr (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-017 figure 16 . negative psrr vs. frequency, rti 10 9 8 7 6 5 4 3 2 1 0 10 change in offset voltage, rti (v) 0.01 0.1 1 warmup time (minutes) 06288-117 figure 17 . change in offset voltage , rti vs. warmup time
ad8250 data sheet rev. c | page 10 of 24 15 10 5 0 ?5 ?10 ?15 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 i b ? i b + i os input bias current and offset current (na) temperature (c) 06288-019 figure 18. input bias current and offset current vs. temperature 140 120 100 80 60 40 20 1 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-020 figure 19. cmrr vs. frequency 140 120 100 80 60 40 20 1 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-021 figure 20. cmrr vs. frequency, 1 k source imbalance 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?50 ?30 ?10 10 30 50 70 90 110 130 06288-049 ? cmrr (v/v) temperature (c) figure 21. cmrr vs. temperature, g = 1 25 ?10 ?5 0 5 10 15 20 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) g = 10 g = 5 g = 2 g = 1 06288-023 figure 22. gain vs. frequency 40 30 20 10 ?10 ?30 0 ?20 ?40 ?10?8?6?4?20246810 06288-024 gain nonlinearity (10ppm/div) output voltage (v) f = 1khz figure 23. gain nonlinearity vs. output voltage, g = 1, r l = 10 k, 2 k, 600
data sheet ad8250 rev. c | page 11 of 24 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 06288-025 output voltage (v) f = 1khz 40 30 20 10 ?10 ?30 0 ?20 ?40 gain nonlinearity (10ppm/div) figure 24 . gain nonlinearity vs. output voltage , g = 2, r l = 10 k ? , 2 k ? , 600 ? ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 06288-026 output voltage (v) f = 1khz 40 30 20 10 ?10 ?30 0 ?20 ?40 gain nonlinearity (10ppm/div) figure 25 . gain nonlinearity vs. o utput voltage , g = 5, r l = 10 k ? , 2 k ? , 600 ? ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 06288-027 output voltage (v) f = 1khz 40 30 20 10 ?10 ?30 0 ?20 ?40 gain nonlinearity (10ppm/div) figure 26 . gain nonlinearity vs. o utput voltage , g = 10, r l = 10 k ? , 2 k ? , 600 ? 16 ?16 ?12 ?8 ?4 0 4 8 12 ?16 ?12 ?8 ?4 0 4 8 12 16 input common-mode voltage (v) output voltage (v) v s = 15v ?13.8v, +6.9v ?13.8v, ?6.9v +13.8v, ?6.9v +13.8v, +6.9v ?3.8v, +1.9v ?3.8v, ?1.9v +3.9v, +1.9v 0v, +3.7v 0v, ?4.0v +3.8v, ?2.1v 0v, +13.8v 0v, ?14v v s = 5v 06288-028 figure 27 . input common - mode voltage range vs. output voltage, g = 1 16 ?16 ?12 ?8 ?4 0 4 8 12 ?16 ?12 ?8 ?4 0 4 8 12 16 input common-mode voltage (v) output voltage (v) v s = 15v ?14.1v, +13.6v ?4.2v, +2.2v +4.3v, +2.1v +4.3v, ?2.1v ?4.2v, ?2.0v 0v, ?4.1v +0v, +3.5v 0v, ?14v 0v, +13.8v ?14.1v, ?13.6v +13.6v, +13.1v +13.6v, ?13.1v v s = 5v 06288-029 figure 28 . input common - mode voltage range vs. output voltage, g = 10 35 30 25 20 15 10 5 0 ?5 ?10 ?15 ?15 ?10 ?5 0 5 10 15 06288-129 input bias current and offset current (na) common-mode voltage (v) i b + i b ? i os figure 29 . input bias current and offset current vs. common - mode voltage
ad8250 data sheet rev. c | page 12 of 24 + v s ?v s +1 +2 ?2 ?1 4 6 8 10 12 14 16 ?40c ?40c +25c +25c +85c +85c +125c input voltage referred to supply voltage (v) supply voltage (v s ) +125c 06288-030 figure 30. input voltage limit vs. supply voltage, g = 1, v ref = 0 v, r l = 10 k 15 ?15 ?10 ?5 0 5 10 ?16 ?12 ?8 ?4 0 4 8 12 16 +v s +in ?in ?v s current (ma) differential input voltage (v) 06288-031 fault condition (over driven input) g = 10 fault condition (over driven input) g = 10 figure 31. fault current draw vs. input voltage, g = 10, r l = 10 k + v s ?v s +0.2 +0.4 +0.6 +0.8 +1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 4 6 8 10 12 14 16 output voltage swing referred to supply voltage (v) supply voltage (v s ) ?40c ?40c +25c +25c +85c +85c +125c +125c 06288-032 figure 32. output voltage swing vs. supply voltage, g = 10, r l = 2 k + v s ?v s +0.2 +0.4 +0.6 +0.8 +1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 4 6 8 10 12 14 16 output voltage swing referred to supply voltage (v) supply voltage (v s ) ?40c +25c +25c +85c +85c +125c +125c ?40c 06288-033 figure 33. output voltage swing vs. supply voltage, g = 10, r l = 10 k 15 10 5 0 ?5 ?10 ?15 100 1k 10k output voltage swing (v) load resistance ( ? ) +125c ?40c ?40c +85c +85c +25c +25c +125c 06288-034 figure 34. output voltage swing vs. load resistance + v s ?0.8 ?0.4 ?2.0 ?1.6 ?1.2 +1.2 +1.6 +2.0 +0.8 +0.4 ?v s 02 6 10 14 4 8 12 16 06288-035 output voltage swing referred to supply voltage (v) output current (ma) +125c +85c +25c ?40c +125c +85c +25c ?40c figure 35. output voltage swing vs. output current
data sheet ad8250 rev. c | page 13 of 24 v out (v) time (s) 2s/div 20mv/div no load 47pf 100pf 06288-036 figure 36 . small signal pulse response for various capacitive loads 06288-037 5v/div 2s/div time (s) 0.002%/div 585ns t o 0.01% 615ns t o 0.001% figure 37 . large signal pulse response and settling time, g = 1, r l = 10 k? 06288-038 5v/div 2s/div time (s) 0.002%/div 605ns t o 0.01% 635ns t o 0.001% figure 38 . large signal pulse response and settling time g = 2, r l = 10 k? 06288-039 5v/div 2s/div time (s) 0.002%/div 605ns t o 0.01% 635ns t o 0.001% figure 39 . large signal pulse response and settling time g = 5, r l = 10 k? 06288-040 5v/div 2s/div time (s) 0.002%/div 648ns t o 0.01% 685ns t o 0.001% figure 40 . large signal pulse response and settling time g = 10, r l = 10 k? v out (v) time (s) 2s/div 20mv/div 06288-042 figure 41 . small signal response g = 1, r l = 2 k?, c l = 100 pf
ad8250 data sheet rev. c | page 14 of 24 v out (v) time (s) 2s/div 20mv/div 06288-043 figure 42 . small signal response g = 2, r l = 2 k?, c l = 100 pf v out (v) time (s) 2s/div 20mv/div 06288-044 figure 43 . small signal response g = 5, r l = 2 k?, c l = 100 pf v out (v) time (s) 2s/div 20mv/div 06288-045 figure 44 . small signal response, g = 10, r l = 2 k?, c l = 100 pf ?50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 10 100 1k 10k 100k 1m 06288-149 thd + n (db) frequency (hz) g = 1 g = 2 g = 5 g = 10 figure 45 . total harmonic distortion + noise vs. frequency, 10 hz to 22 khz band - pass filter, r l = 2 k ? ?50 ?60 ?70 ?80 ?90 ?100 ?110 10 100 1k 10k 100k 1m 06288-150 frequency (hz) g = 1 g = 2 g = 5 g = 10 thd + n (db) figure 46 . total harmonic distortion + noise vs. frequency, 10 hz to 500 khz band - pass filter , r l = 2 k ?
data sheet ad8250 rev. c | page 15 of 24 theory of operation 10k ? 10k ? 10k ? 10k ? ref out a3 ? in +in wr 2.2k ? 2.2k ? + v s + v s ?v s ?v s +v s ?v s +v s ?v s a1 a0 2.2k ? dgnd a1 a2 digital gain control 2.2k ? +v s ?v s +v s ?v s +v s ?v s +v s ?v s 0 6288-054 figure 47. simplified schematic the ad8250 is a monolithic instrumentation amplifier based on the classic, 3-op-amp topology as shown in figure 47. it is fabricated on the analog devices, inc., proprietary i cmos? process that provides precision, linear performance, and a robust digital interface. a parallel interface allows users to digitally program gains of 1, 2, 5, and 10. gain control is achieved by switching resistors in an internal, precision resistor array (as shown in figure 47). although the ad8250 has a voltage feedback topology, the gain bandwidth product increases for gains of 1, 2, and 5 because each gain has its own frequency compensation. this results in maximum bandwidth at higher gains. all internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow thd. laser trimmed resistors allow for a maximum gain error of less than 0.03% for g = 1 and minimum cmrr of 98 db for g = 10. a pinout optimized for high cmrr over frequency enables the ad8250 to offer a guaranteed minimum cmrr over frequency of 80 db at 50 khz (g = 1). the balanced input reduces the parasitics that, in the past, adversely affected cmrr performance. gain selection logic low and logic high voltage limits are listed in the specifications section. typically, logic low is 0 v and logic high is 5 v; both voltages are measured with respect to dgnd. see table 2 for the permissible voltage range of dgnd. the gain of the ad8250 can be set using two methods. transparent gain mode the easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to a0 and a1. figure 48 shows an example of this gain setting method, referred to through- out the data sheet as transparent gain mode. tie wr to the negative supply to engage transparent gain mode. in this mode, any change in voltage applied to a0 and a1 from logic low to logic high, or vice versa, immediately results in a gain change. table 5 is the truth table for transparent gain mode, and figure 48 shows the ad8250 configured in transparent gain mode. +15 v ?15v ?15v a0 a1 wr +in +5v +5v ?in 10 f0.1f 10 f0.1f g = 10 dgnd dgnd ref ad8250 06288-055 note: 1. in transparent gain mode, wr is tied to ? v s . the voltage levels on a0 and a1 determine the gain. in this example, both a0 and a1 are set to logic high, resulting in a gain of 10. figure 48. transparent gain mode, a0 and a1 = high, g = 10
ad8250 data sheet rev. c | page 16 of 24 table 5. truth table logic leve ls for transparent gain mode wr a1 a0 gain ?v s low low 1 ?v s low high 2 ?v s high low 5 ?v s high high 10 latched gain mode some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same pcb. in such cases, devices can share a data bus. the gain of the ad8250 can be set using wr as a latch, allowing other devices to share a0 and a1. figure 49 shows a schematic using this method, known as latched gain mode. the ad8250 is in this mode when wr is held at logic high or logic low, typically 5 v and 0 v, respectively. the voltages on a0 and a1 are read on the downward edge of the wr signal as it transitions from logic high to logic low. this latches in the logic levels on a0 and a1, resulting in a gain change. see the truth table in table 6 for more information on these gain changes. +15 v ?15v a0 a1 wr +in ?in 10 f0.1f 10 f0.1f dgnd dgnd ref ad8250 a0 a1 wr +5v +5v +5v 0v 0v 0v g = previous state g = 10 06288-056 + ? note: 1. on the downward edge of wr, as it transitions from logic high to logic low, the voltages on a0 and a1 are read and latched in, resulting in a gain change. in this example, the gain switches to g = 10. figure 49. latched gain mode, g = 10 table 6. truth table logic le vels for latched gain mode wr a1 a0 gain high to low low low change to 1 high to low low high change to 2 high to low high low change to 5 high to low high high change to 10 low to low x 1 x 1 no change low to high x 1 x 1 no change high to high x 1 x 1 no change 1 x = dont care. on power-up, the ad8250 defaults to a gain of 1 when in latched gain mode. in contrast, if the ad8250 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on a0 and a1 at power-up. timing for latched gain mode in latched gain mode, logic levels at a0 and a1 have to be held for a minimum setup time, t su , before the downward edge of wr latches in the gain. similarly, they must be held for a minimum hold time of t hd after the downward edge of wr to ensure that the gain is latched in correctly. after t hd , a0 and a1 can change logic levels, but the gain does not change (until the next downward edge of wr ). the minimum duration that wr can be held high is t wr -high , and the minimum duration that wr can be held low is t wr -low . digital timing specifications are listed in table 2. the time required for a gain change is dominated by the settling time of the amplifier. a timing diagram is shown in figure 50. when sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the ad8250. feedthrough can be minimized by decreasing the edge rate of the logic signals. furthermore, careful layout of the pcb also reduces coupling between the digital and analog portions of the board. pull-up or pull-down resistors should be used to provide a well-defined voltage at the a0 and a1 pins. a0, a1 wr t su t hd t wr-high t wr-low 0 6288-057 figure 50. timing diagram for latched gain mode
data sheet ad8250 rev. c | page 17 of 24 power supply regulation and bypassing the ad8250 has high psrr. however, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect per- formance. as in all linear circuits, bypass capacitors must be used to decouple the amplifier. place a 0.1 f capacitor close to each supply pin. a 10 f tantalum capacitor can be used farther away from the part (see figure 51) and, in most cases, it can be shared by other precision integrated circuits. ad8250 + v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s dgnd out dgnd a0 a1 wr 06288-058 figure 51. supply decoupling, ref, and output referred to ground input bias current return path the ad8250 input bias current must have a return path to its local analog ground. when the source, such as a thermocouple, cannot provide a return current path, one should be created (see figure 52). thermocouple +v s ref ?v s ad8250 capacitively coupled +v s ref c c ?v s ad8250 transformer +v s ref ?v s ad8250 incorrect capacitively coupled +v s ref c r r c ?v s ad8250 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? ad8250 transformer +v s ref ?v s ad8250 correct 06288-059 figure 52. creating an i bias return path input protection all terminals of the ad8250 are protected against esd. note that 2.2 k series resistors precede the esd diodes as shown in figure 47. the resistors limit current into the diodes and allow for dc overload conditions 13 v above the positive supply and 13 v below the negative supply. an external resistor should be used in series with each input to limit current for voltages greater than 13 v beyond either supply rail. in either scenario, the ad8250 safely handles a continuous 6 ma current at room temperature. for applications where the ad8250 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as bav199ls, fjh1100s, or sp720s, should be used.
ad8250 data sheet rev. c | page 18 of 24 reference terminal the reference terminal, ref, is at one end of a 1 0 k resistor (see figure 47 ). the instrumentation amp lifier output is referenced to the voltage on the ref terminal; this is useful when the output signal needs to be offset to voltages other than its local analog ground . for example, a voltage source can be tied to the ref pin to level shift the output so t hat the ad8250 can interface with a single - supply adc. the allowable reference voltage range is a function of the gain, common - mode input, and supply voltages. the ref pin should not exceed either +v s or ?v s by more than 0.5 v. for best performance, especially in cases where the output is not measured with respect to the ref terminal, source imped - ance to the ref terminal should be kept low because parasitic resistance can adversely affect cmrr and gain accuracy. incorrect ad8250 v ref correct ad8250 op1177 + ? v ref 06288-060 figure 53 . driving the reference pin common - mode input voltage r ange the 3 - op - amp architecture of the ad8250 applies gain and then removes the common - mode voltage. therefore, internal nodes in the ad8250 experience a c ombination of both the gained signal and the common - mode signal. this combined signal can be limited by the voltage supplies even when the individual input and o utput signals are not. figure 27 and figure 28 show the allowable common - mode input voltage ranges for various output voltages, supply voltages, and gains. layout grounding in mixed - signal circuits, low level analog signals need to be isolated from the noisy digital environment. designing with the ad8250 is no exception. its supply voltages are ref erenced to an analog ground . i t s digital circuit is referenced to a digital ground . although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires an d pc b can cause e rror s . therefore, use separate analog and digital ground planes . analog and digital ground should meet at only one point : star ground. the output voltage of the ad8250 develop s with respect to the potential on the reference terminal. tak e c are to tie ref to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground. coupling noise to prevent coupling noise onto the ad8250 , do the follow ing guidelines: ? do not run digital lines under the device. ? r un the analog ground plane under the ad8250 . ? shield fast switching signals with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths. ? avoid crossover of digital and analog signals. ? connect digital and analog ground at one point only (typically under the adc). ? u se the large traces on power supply lines to ensure a low impedance path. decoupling is necessary ; follow the guidelines listed in the power supply r egulation and bypassing section. common - mode rejection the ad8250 has high cmrr over frequency , giving it greater immunity to disturbances , such as line noise and its associated harmonics , in contrast to typical instrumentation amp lifier s whose c mrr falls off around 200 hz. t ypical instrumentat ion amplifier s often need common - mode filters at the ir inputs to compensate for this shortcoming. the ad8250 is able to reject cmrr over a greater frequency range, reducing the need for input common - mode filtering. careful board layout maximizes system performance. to maintain high cmrr over frequency, lay out the input traces symmetrically. ensure that the traces maintain resistive and capacitive balance; this holds for additional pcb metal layers under the input pi ns and traces . source resistance and capaci - tance should be placed as close to the inputs as possible. should a trace cross the inputs ( from an other layer), route it perpendicular to the input traces.
data sheet ad8250 rev. c | page 19 of 24 rf interference rf rectification is often a problem when amplifiers are used in applications where there are strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low-pass rc network placed at the input of the instrumentation amplifier, as shown in figure 54. the filter limits the input signal bandwidth according to the following relationship: )(22 1 c d diff ccr filterfreq ? ? ? c cm rc filterfreq ? 2 1 ? where c d 10 c c . r r ad8250 +15 v +in ?in 0.1f 10f 10f 0.1f ref ?15v c d c c c c 0 6288-061 out figure 54. rfi suppression values of r and c c should be chosen to minimize rfi. a mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the ad8250. by using a value of c d that is 10 times larger than the value of c c , the effect of the mismatch is reduced and performance is improved. driving an adc an instrumentation amplifier is often used in front of an adc to provide cmrr. usually, instrumentation amplifiers require a buffer to drive an adc. however, the low output noise, low distortion, and low settle time of the ad8250 make it an excellent adc driver. in this example, a 1 nf capacitor and a 100 resistor create an antialiasing filter for the ad7612 . the 1 nf capacitor stores and delivers the necessary charge to the switched capacitor input of the adc. the 100 series resistor reduces the burden of the 1 nf load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the ad7612. selecting too small a resistor improves the correlation between the voltage at the output of the ad8250 and the voltage at the input of the ad7612 but may destabilize the ad8250. a trade- off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. 0.1 f 0.1 f 1nf 100 ? ad7612 adr435 +12v ?12v +5v +15 v ?15v a0 a1 wr +in ? in 10 f0.1f 10 f0.1f ref ad8250 06288-062 dgnd dgnd figure 55. driving an adc
ad8250 data sheet rev. c | page 20 of 24 applications differential output in certain applications, it is necessary to create a differential signal. high resolution adcs often require a differential input. in other cases, transmission over a long distance can require differential signals for better immunity to interference. figure 57 shows how to configure the ad8250 to output a differential signal. an op amp, the ad817 , is used in an inverting topology to create a differential voltage. v ref sets the output midpoint according to the equation shown in the figure. errors from the op amp are common to both outputs and are thus common mode. likewise, errors from using mismatched resistors cause a common-mode dc offset error. such errors are rejected in differential signal processing by differential input adcs or instrumentation amplifiers. when using this circuit to drive a differential adc, v ref can be set using a resistor divider from the adc reference to make the output ratiometric with the adc. setting gains with a microcontroller +15 v micro- controller ?15v a0 a1 wr +in ? in 10 f0.1f 10 f0.1f ref ad8250 06288-063 + ? dgnd dgnd figure 56. programming gain using a microcontroller +12 v ?12v a0 a1 wr +in 10 f 0.1 f 10 f 0.1 f ad8250 ref g = 1 0.1f 4.99k ? 4.99k ? ad817 0.1f +12v ?12v v ref 0v v out a = v in + v ref 2 2 v out b = ?v in + v ref +2.5v ?2.5v 0v +2.5v ?2.5v 0v time amplitude 0v time amplitude +5 v ?5v amplitude 10pf +12v ?12v v in 06288-064 + ? +? dgnd dgnd figure 57. differential output with level shift
data sheet ad8250 rev. c | page 21 of 24 data acquisition the ad8250 makes an excellent instrumentation amplifier for use in data acquisition systems. its wide bandwidth, low distortion, low settling time , and low noise enable it to condition signals in front o f a variety of 16 - bit adcs. figure 59 shows a schematic of the ad825 x data acquisition demo nstration boa rd . the quick slew rate of the ad8250 allows it to condition rapidly changing signals from the multiplexed inputs. an fpga co ntrol s the ad7612 , ad8250, and adg1209 . in addition, mechanical switc hes and jumpers allow users to pin strap the gains when in transparent gain mode. this system achieved ? 111 db of thd at 1 khz and a signal - to - noise ratio of 91 db during testing , as shown in figure 58. 0 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5 10 15 20 25 30 35 40 45 50 amplitude (db) frequency (khz) 06288-066 figure 58 . fft of the ad825x daq demo board u sing the ad8250, 1 khz s ignal 06288-065 ad8250 2 +in ?in a1 a0 out ref ?v s +v s dgnd 5 3 4 9 1 7 10 11 12 13 14 15 16 6 2 s1a en s2a s3a s4a s1b s2b db gnd da s3b s4b a0 a1 v ss v dd jmp jmp jmp +12v ?12v +12v ?12v jmp jmp ?v s +5v +5v dgnd 806 806 806 806 806 806 806 806 0 0 49.9 0 ?ch1 +ch1 +ch2 ?ch2 +ch3 ?ch3 +ch4 ?ch4 1nf 2k 2k 0.1f gnd +12v ?12v + + 10f 10f 0.1f c d c c c c c3 0.1f c4 0.1f +5v +5v dgnd dgnd r8 2k +in ad7612 adr435 adg1209 dgnd altera epf6010atc144-3 8 0 0 1 10 6 wr 9 4 5 8 3 7 + ? dgnd 2k ? dgnd figure 59 . schematic of adg1209 , ad8250, and ad7612 in the ad825x daq demo board
ad8250 data sheet rev. c | page 22 of 24 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 60. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad8250armz C40c to +85c 10-lead mini small outline package [msop] rm-10 h00 ad8250armz-rl C40c to +85c 10-lead mini small outline package [msop] rm-10 h00 AD8250ARMZ-R7 C40c to +85c 10-lead mini small outline package [msop] rm-10 h00 ad8250-evalz evaluation board 1 z = rohs compliant part.
data sheet ad8250 rev. c | page 23 of 24 notes
ad8250 data sheet rev. c | page 24 of 24 notes ? 2007 C 2013 analog devices , inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06288 - 0- 5/13(c)

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